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STRUCTURE NAME OF PRODUCT TYPE FUNCTION
Silicon Monolithic Integrated Circuit DC-AC Inverter Control IC
36V High voltage process 1ch control with Full-Bridge Lamp current and voltage sense feed back control Sequencing easily achieved with Soft Start Control Short circuit protection with Timer Latch Under Voltage Lock Out Mode-selectable the operating or stand-by mode by stand-by pin For master IC, Synchronous operating with slave IC BURST mode controlled by PWM and DC input Output liner Control by external DC voltage
Absolute Maximum RatingsTa = 25
Parameter Supply Voltage BST pin SW pin BST-SW voltage difference Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Power Dissipation
*
Symbol VCC BST SW BST-SW Topr Tstg Tjmax Pd
Limits 36 40 36 15 -40+85 -55+150 +150 1062*
Unit V V V V mW
Pd derate at 8.5mW/ for temperature above Ta = 25 (When mounted on a PCB 70.0mmx70.0mmx1.6mm)
Operating condition
Parameter Supply voltage BST voltage BST-SW voltage difference DRIVER frequency BCT oscillation frequency Symbol VCC BST BST-SW FOUT fBCT Limits 8.530.0 5.037.5 5.014.0 30110 0.051.00 Unit V V V kHz kHz
REV. A
2/4 Electric CharacteristicsTa=25VCC=24VSTB=UVLO=3.0V
Limits TYP. 5.0 6.3 2.25 0.110 7.50 1.50 2.2 0.20 1.50 85 2 0.5 1.5/BRT 300 1.25 VREFIN 1.25 50 0.625 0.50 4.0 150 300 3.5 9.0 3.5 9.0 48.5 200 60 4.0 2.1 4.0 0.20 4.0 150 300
Parameter WHOLE DEVICE Operating current Stand-by current STAND BY CONTROL Stand-by voltage H Stand-by voltage L UVLO BLOCK Operating voltage (UVLO) Hesteresis width (UVLO) REG BLOCK REG output voltage REG source current OSC BLOCK RT pin Voltage Soft start current SS operation start Voltage SS term END Voltage SRT ON resistance BOSC BLOCK BOSC Max voltage BOSC Min voltage BOSC constant current BOSC frequency FEED BACK BLOCK IS threshold voltage 1 IS threshold voltage 2 VS threshold voltage IS source current 1 IS source current 2 VS source current IS COMP detect voltage 1 IS COMP detect voltage 2 VREF input voltage range DUTY BLOCK High voltage Low voltage DUTY-OUT sink resistance DUTY-OUT source resistance OUTPUT BLOCK LN output sink resistance LN output source resistance HN output sink resistance HN output source resistance MAX DUTY OFF period Drive output frequency TIMER LATCH BLOCK Timer Latch setting voltage Timer Latch setting current COMP BLOCK
COMP over voltage detect voltage
Symbol Icc1 Icc2 VstH VstL Vuvlo Vuvlo VREG IREG VRT ISS VSS_ST VSS_ED RSRT VBCTH VBCTL IBCT fBCT VIS1 VIS2 VVS IIS1 IIS2 IVS VISCOMP1 VISCOMP2 VREFIN
VDUTY-OUTH VDUTY-OUTL
RDUTY-OUT_sink RDUTY-OUT_source
MIN. 2 -0.3 2.16 0.085 7.35 20 1.05 1.7 0.18 1.35 1.94 0.4 1.35/BRT 291 1.225 1.22 40 0.606 0.6 3.8 1.8 4.5 1.8 4.5 46.0 100 57.9 3.88 1.6 3.88 0.15 3.8
MAX. 9.0 20 VCC 0.8 2.34 0.135 7.65 1.95 2.7 0.22 1.65 170 2.06 0.6 1.65/BRT 309 1.275 VIS1 1.28 0.9 60 0.9 0.644 1.6 4.2 0.5 300 600 7.0 18.0 7.0 18.0 49.5 400 62.1 4.12 2.6 4.12 0.25 4.2 0.5 300 400
Unit mA A V V V V V mA V A V V V V A Hz V V V A A A V V V V V % ns kHz V A V V V V
Conditions
FOUT=60kHz, FB=GND, BST=OPEN
System System
fBCT=0.3kHz fBCT=0.3kHz VBCT=0.2V (BRT=37.8k BCT=0.047F)
VREF applying voltage DUTY=2.2V DUTY=0V IS=1.0V VREFIN1.25V VREFIN= 1V No effect at VREF1.25V
RsinkLN RsourceLN RsinkHN RsourceLN MAX DUTY TOFF FOUT VCP ICP VCOMPH VCOMPH VCT_SYNCH VCT_SYNCL
RSYNC_OUT_sink
RSYNC_OUT_source
VBST-VSW=7.0V VBST-VSW=7.0V FOUT=60kHz RT=21k
VSS1.65V
Hysterisis width (COMP) ((Synchronous Block)) High voltage Low voltage CT_SYNC_OUT sink resistance CT_SYNC_OUT source resistance
This product is not designed to be radiation-resistant.
REV. A
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Package Dimensions
Pin Description
Device Mark
PIN No. 1
PIN NAME PGND LN2 HN2 SW2 BST2
DUTY_OUT CT_SYNC_OUT
FUNCTION
Ground for FET drivers NMOS FET driver NMOS FET driver Lower rail voltage for HN2 output Boot-Strap input for HN2 output BURST signal output pin CT synchronous signal output pin External adjusting External adjusting GROUND External adjusting External adjusting capacitor from BCT to GND for the BURST triangle oscillator resistor from BRT to GND for the BURST triangle oscillator resistor from SRT to RT for the start-up triangle oscillator resistor from RT to GND for the triangle oscillator
(Include BURR : MAX 10.35)
2 3 4
BD9215AFV
5 6 7 8
SRT RT GND BCT BRT DUTY STB CP VREF VS IS FB SS COMP VCC UVLO REG BST1 SW1 HN1 LN1
Lot No.
9 10 11 12 13 14
Control PWM mode and BURST mode Stand-by switch External capacitor from CP to GND for Timer Latch Reference voltage input pin for Error amplifier Error amplifier input Error amplifier input Error amplifier output External capacitor from SS to GND for Soft Start Control Over voltage detect pin Supply voltage input External Under Voltage Lock Out Internal regulator output Boot-Strap input for HN1 output Lower rail voltage for HN1 output NMOS FET driver NMOS FET driver
SSOP-B28 (Unit:mm)
15 16 17
Block Diagram
18 19 20 21 22 23 24 25 26 27 28
REV. A
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NOTE FOR USE
. This product is produced with strict quality control, but might be destroyed if used beyond its absolute maximum ratings. Once IC is destroyed, failure mode will be difficult to determine, like short mode or open mode. Therefore, physical protection countermeasure, like fuse is recommended in case operating conditions go beyond the expected absolute maximum ratings. . The circuit functionality is guaranteed within of ambient temperature operation range as long as it is within recommended operating range. The standard electrical characteristic values cannot be guaranteed at other voltages in the operating ranges, however the variation will be small. . Mounting failures, such as misdirection or miscounts, may harm the device. . A strong electromagnetic field may cause the IC to malfunction. . The GND pin should be the location within 0.3V compared with the PGND pin. ALL Pin (except SW1, SW2, BST1, BST2, HN1, HN2,) Voltage should be under VCC voltage +0.3V even if the voltage is under each terminal ratings. . BD9215AFV incorporate a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is designed only to shut the IC off to prevent runaway thermal operation. It is not designed to protect the IC or guarantee its operation of the thermal shutdown circuit is assumed. . When modifying the external circuit components, make sure to leave an adequate margin for external components actual value and tolerance as well as dispersion of the IC. . About the external FET, the parasitic Capacitor may cause the gate voltage to change, when the drain voltage is switching. Make sure to leave adequate margin for this IC variation. . Under operating CP charge (under error mode) analog dimming and burst dimming are not operate. 10. Under operating Slow Start Control (SS is less than 1.5V), It does not operate Timer Latch. 11. By STB voltage, BD9215AFV are changed to 2 states. Therefore, do not input STB pin voltage between one state and the other state (0.82.0V). 12. The pin connected a connector need to connect to the resistor for electrical surge destruction. 13. This IC is a monolithic IC which (as shown is Fig-1) has P+ substrate and between the various pins. A P-N junction is formed from this P layer of each pin. For example, the relation between each potential is as follows, (When GND > PinB and GND > PinA, the P-N junction operates as a parasitic diode.) (When PinB > GND > PinA, the P-N junction operates as a parasitic transistor.) Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can result in mutual interference among circuits as well as operation faults and physical damage. Accordingly you must not use methods by which parasitic diodes operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin.
Resistance (PinA) (PinB) C Transistor (NPN) B E GND P P N P substrate GND Parasitic diode N P P substrate GND Parasitic diode (PinB) (PinA) B Parasitic diode GND
N
N
C E GND
Other adjacent components
Parasitic diode
Fig-1 Simplified structure of a Bipolar IC
REV. A
Notice
Notes
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